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Contents : IEEE ELECTRON DEVICE LETTERS VOL. 22 NO. 3 MARCH 2001 139 RF Power LDMOSFET on SOI James G. Fiorenza Member IEEE Dimitri A. Antoniadis Fellow IEEE and Jes s A. del Alamo Senior Member IEEE Abstract We have fabricated a SOI laterally diffused MOSFET that is designed for use in radio frequency power amplifiers for wireless system-on-a-chip applications. The device is fabricated on a thin-film SOI wafer using a process that is suitable for integration with SOI CMOS. An under-source body contact is implemented and both a high breakdown voltage and a high are attained. The device performance compares favorably with bulk silicon rf power MOSFETs. For a gate length of 0.7 m the device is 14 GHz max is 18 GHz and the breakdown voltage approaches 25 V. Fig. 1. Cross section of the rf power SOI LDMOSFET that was fabricated. Index Terms LDMOSFET RF CMOS RF SOI. I. INTRODUCTION T HIS work describes a laterally diffused MOSFET (LDMOSFET) on thin-film silicon on insulator (SOI) that is designed for use in the transmitter rf power amplifier in portable wireless applications. Bulk silicon LDMOSFETs have been very successful in these applications 1 and implementation of a LDMOSFET in thin-film SOI may enable power amplifiers with improved gain efficiency and bandwidth. Moreover implementation of a LDMOSFET in thin-film SOI may allow the integration of the rf power amplifier (PA) into a wireless system-on-a-chip in which all of the digital analog and rf circuits of a wireless system are integrated on to a single die. While thin-film SOI is a promising technology platform for a single chip system the realization of a high performance rf power device in thin-film SOI is recognized as particularly challenging 2 . This paper demonstrates a LDMOSFET on SOI that compares well with bulk silicon LDMOSFETs. In this device the body contact which is critical to attaining a high breakdown voltage is fabricated beneath the source. The intrinsic performance of this SOI LDMOSFET is as good or better than any know rf power MOSFET on SOI. There is limited previous work on the development of MOSFET s on thin-film SOI for RF PA applications. Matsumoto et al. demonstrated a Quasi-SOI device with a high breakdown voltage and good rf performance but its exotic fabrication process makes it incompatible with CMOS 3 . In 4 a rf PA is demonstrated on SOI that utilizes a technology that is adapted from standard SOI CMOS. The breakdown voltage of the technology is low and the PA that is demonstrated operates from a power supply of only 1.8 V too low to be useful in most modern wireless communication systems. In recent work 5 a SOI LDMOSFET was fabricated but it uses an inferior stripped body contact. This body contact increases the gate and drain capacitance for a given effective gate width resulting Manuscript received October 19 2000. This work was supported by the Semiconductor Research Corporation. The review of this letter was arranged by Editor K. De Meyer. The authors are with the Massachusetts Institute of Technology Cambridge MA 02139 USA (e-mail: fiorenza@mtl.mit.edu). Publisher Item Identifier S 0741-3106(01)01935-8. in a reduced transconductance and frequency response. In 6 the intrinsic performance of the SOI MOSFET that was fabricated was poor because of the lack of a body contact and high overlap capacitance. The approach demonstrated in this letter addresses these weaknesses and yields unprecedented performance. II. DEVICE FABRICATION A cross section of the LDMOSFET that is demonstrated is shown in Fig. 1. The partially depleted SOI LDMOSFETs were full-dose SIMOX wafers with an acfabricated on p-type tive silicon thickness of 200 nm a buried oxide of 400 nm and a resistivity of 10 20 -cm. The process was designed so that the SOI LDMOSFET can be integrated into an SOI CMOS process. The silicon thickness is the same as the film thickness in mainstream SOI CMOS 7 . LOCOS isolation was used. The shortest n polysilicon gate is 0.7 m the n lightly doped drain (LDD) region is 0.5 m and the gate oxide thickness is 30 nm. The lateral body doping profile was formed by masking the drain of the device implanting the source with boron of dose cm and energy 25 KeV and annealing the wafers for 300 min at 1000 C. The n LDD region was created by a phosphorous cm and energy 55 KeV. The n implant of dose source and drain regions were formed by a masked implant of cm and energy 25 KeV. The n implant mask dose defines the length of the n region. The dopants were activated by a 20 s 1000 C RTA process. After processing the silicon thickness beneath the gate is 180 nm and the n junction depth beneath the source is 100 nm. III. RESULTS AND DISCUSSION The output characteristics of a typical device are shown in Fig. 2. There is no sign of a kink or indication of impact ionization up to a drain voltage of 7 V. The transfer characteristics are shown in Fig. 3. The device t

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