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Contents : Reliability-Aware OS Support for FPGA-Based Systems Extended Abstract Authors: M. Kandemir (PSU) and G. Chen (PSU) Reconfigurable computing systems have shown the ability to greatly accelerate program execution providing a high-performance alternative to software-only implementations and a programmable alternative to ASICs. While prior research have addressed architecture design programming and compilation issues there is still not much consensus on what kind of operating system (OS) support should be provided for reconfigurable architectures. Prior OS related work has evaluated different scheduling algorithms on an FPGA based platform and found that different OS scheduling algorithms can generate different results. Increasing soft-error rates force designers to look at the OS support for FPGAs from a reliability viewpoint as well. In particular one may want to tailor existing OS services according to the reliability requirements of the execution environment. Our Approach The focus of this paper is to design and evaluate a reliability-aware OS scheduler for FPGA based environments. The primary mechanism through which the OS tries to provide reliability is task duplication under QoS guarantees. To achieve this the proposed approach operates as follows: vj vi (a ) (b ) 1) The application programmer indicates Figure 1. (a) An example STG (note that node vj depends on which data structures are critical from node vi). (b) Two STGs and data dependences between them the reliability viewpoint using (shown as dashed arrows). annotations (annotation step). 2) The application programmer also indicates the tolerable latency during application execution as a result of the reliability provided (QoS specification step). 3) An automatic application code analyzer analyzes the source code and identifies tasks (task identification step). 4) Based on how these tasks operate on critical data they are ranked (i.e. ordered from the most important task to the least important one task ranking step). 5) The OS scheduler is modified such that whenever there is opportunity the OS duplicates tasks (that run on the FPGA device) to provide resilience to soft errors (scheduling step). While our current implementation focuses only on error detection not error correction it is possible to incorporate error correction into our framework by duplicating a task twice instead of once and then voting. We represent each process (task) to be scheduled by a subtask graph (henceforth referred to as STG). Each node of this graph represents a process code portion (subtask) that will be executed in a single quantum of time once it gets scheduled. Note that depending on the computation being performed by the node each node may require a different amount of FPGA space (i.e. when it is mapped to the FPGA it can demand a different size rectangular region than the others). A directed edge (arrow) from a node vi STG to another node vj STG indicates a data or control dependence from vi to vj that is vj cannot be executed before vi (they can be pipelined in some cases however we do not consider pipelining in this paper). Figure 1(a) depicts a typical STG for a process (task). Since one of the objectives of any FPGA-based system is to maximize FPGA utilization the OS scheduler should be able to schedule nodes from the STGs of different applications. It should be observed that while one may have the option of executing each process in a strict order (i.e. not start executing the next one while the previous one is still running) this may not be a very good idea since dependences between the nodes of the STG in question would prevent full utilization of the available FPGA space. Therefore our approach is oriented towards maximizing FPGA space utilization by parallel execution of multiple processes. Also since our processes are extracted from the same application there might be data dependences between them (as shown in Figure 1(b)). During the scheduling whenever the available FPGA space is not fully utilized by concurrently-executing tasks the reliability-aware scheduler starts duplicating tasks starting with the most important ones. It also schedules a checker task (per duplicated task) whose sole purpose is the check the outputs of the primary task and the duplicate and signal an error when the two outputs differ. It is to be noted that just the fact that we have available space on the FPGA for duplications does not necessarily mean that the duplications will not affect the overall execution time. They can still cause performance degradation due to external runtime conditions and data/control dependences between the tasks that could not be captured by our automatic static analysis (that extracts tasks and dependences between them). Therefore the proposed scheduler also takes a QoS parameter as input which indicates the maximum tolerable increase in execution time of the application. Whenever the scheduler p

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